The present invention relates to a semiconductor storage device, and more particularly, to a semiconductor storage device that incorporates, for example, an SRAM (Static Random Access Memory) as a storage cell.
In recent years, the processes for semiconductor devices have become finer. However, as the processes for semiconductor devices have become finer, the driving ability of a single transistor has been decreased, which causes problems such as deterioration in write characteristics and data retention ability of an SRAM (Static Random Access Memory). In this regard, Japanese Unexamined Patent Application Publication Nos. H08-17186, 2006-85786, and 2008-90958, for example, disclose techniques for improving the write characteristics or data retention characteristics of the SRAM.
A semiconductor storage device disclosed in Japanese Unexamined Patent Application Publication No. H08-17186 includes capacitors having one end connected to one side of a storage node of a flip-flop constituting a memory cell, and having the other end connected to a bit line that is connected to the other side of the storage node through a transfer transistor. The semiconductor storage device disclosed in Japanese Unexamined Patent Application Publication No. H08-17186 can improve the data retention ability by providing the capacitors. However, even when the capacitors are provided in the semiconductor storage device, the write operation margin cannot be improved.
A semiconductor storage device disclosed in Japanese Unexamined Patent Application Publication No. 2006-85786 includes a plurality of static memory cells which are provided so as to respectively correspond to a plurality of word lines and a plurality of complementary bit lines; a plurality of memory cell power supply lines which supply an operating voltage for each of a plurality of memory cells respectively connected to the plurality of complementary bit lines; a plurality of power supply circuits including resistor means which supplies a power supply voltage so as to respectively correspond to the memory cell power supply lines; and a precharge circuit which supplies the complementary bit lines with a precharge voltage corresponding to the power supply voltage. The memory cell power supply lines each include a coupling capacitor that receives a write signal from the corresponding complementary bit line. In the semiconductor storage device disclosed in Japanese Unexamined Patent Application Publication No. 2006-85786, the coupling capacitors and the power supply circuits can improve the write operation margin and the data retention ability.
A semiconductor storage device disclosed in Japanese Unexamined Patent Application Publication No. 2008-90958 includes an SRAM cell including first and second drive transistors, which constitute a pair of inverters, and a voltage generation circuit which applies a voltage having a value lower or higher than a ground voltage to one end of a current path of the first and second drive transistors. In the semiconductor storage device disclosed in Japanese Unexamined Patent Application Publication No. 2008-90958, the voltage generation circuit improves the write operation margin and the data retention ability.